A simple setup to feed AIS data to Marine Traffic with a Raspberry Pi and USB SDr

This document assumes that you have performed the following tasks:. If you have not performed the tasks described above, refer to the SDK’s getting starting guides for more information. The Custom Platform provides the board support package. Typically, the board manufacturer develops the Custom Platform that supports a specific OpenCL board. The offline compiler targets the Custom Platform when compiling an OpenCL kernel to generate a hardware programming image. The host then runs the host application, which usually programs and executes the hardware image onto the FPGA. In a sequential implementation of a program for example, on a conventional processor , the program counter controls the sequence of instructions that are executed on the hardware, and the instructions that execute on the hardware across time. Programs are interpreted as a series of connections representing the data dependencies. An OpenCL kernel source file. The offline compiler groups one or more kernels into a temporary file and then compiles this file to generate the following files and folders:.

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ASIC Vendors developed design kits and qualified the simulation libraries for these tools in order to sign-off on the expected function and timing of their designs. Sign-off simulation in that day was a single process, run with full timing, thereby verifying function and timing simultaneously. As this was computationally expensive, it could not scale as designs grew larger with each process node.

The 90s: Function versus Timing With full-timing sign-off simulation running out of steam, the industry looked for faster simulation methods that used unit timing or cycle-based simulation. In addition, full-timing simulation did not check every timing condition in the design, leading to the possibility of timing errors slipping through the sign-off process. Fortunately, synthesized blocks were already using static timing verification, since it was built into Design Compiler, so a path existed to expand timing verification to full-chip with the introduction of PrimeTime.

With full-chip sign-off timing verification now available, function and timing could be handled separately. However, a very important requirement to enable this abstraction was that designs had to be fully synchronous. This was fine for RTL but started to break down at the gate level. Fortunately, the synchronous nature of these designs enabled another abstraction — formally verifying that a gate-level design is functionally equivalent to the original RTL source, thus creating the market for formal equivalence checking.

This separated verification of the design intent — primarily performed dynamically — from verification of implementation correctness for both function and timing — primarily performed statically using equivalence checking and timing analysis. Thus, the split between dynamic and static verification fell along the lines between intent and implementation.

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A small investment for most that would give you the ability to have a lot more AIS sites around the world. That’s actually a pretty good idea. We tried a few SDR solutions on the Pi a while back but it wasn’t working reliably and. I think I mnaged to sort that out today, similar to ansers further below so wont repeat that. I will still try and sort that outbut it looks like fairly usefull application. In all our tests here both failed to complile without errors.

This is rather complicated and untried. As the dongle warms up this value may change so check again after some time. You can then pipe AIS messages to MarineTraffic using “socat” sudo apt-get install socat using the command below where 1. I am no raspberry pi expert so optimisations could be made for sure. I’m happy to make my SD card image available to anyone who wants a copy, but I don’t have sufficient hosting for the image file.

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Recommended Specification 11 October A diff of changes from the previous draft is available at this link. Please refer to the errata for this document, which may include some normative corrections. All rights reserved. This work is protected under Title 17 of the United States Code. Reproduction and dissemination of this work with changes is prohibited except with the written permission of the International Digital Publishing Forum IDPF.

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